This invention relates to integrated circuit manufacture and, in particular, to metal-based capping of interconnect metallization.
In damascene processing metallization is employed to form electrical interconnects in an integrated circuit substrate by metal-filling of interconnect features such as vias and trenches formed in the substrate. If the metal deposited on such a substrate is Cu, it can diffuse rapidly into the Si substrate and dielectric films as, for example, SiO2 or low k dielectrics. Copper can also diffuse into a device layer built on top of a substrate in multilayer device applications. Such diffusion can be detrimental to the device because it can cause electrical leakage in substrates, or form an unintended electrical connection between two interconnects resulting in an electrical short. And the corresponding diffusion out of the interconnect feature can disrupt electrical flow therethrough.
Metal deposited on the substrate also has a tendency to migrate out of the interconnect feature when electrical current passes through the feature in service. Electron bombardment of the metal moves the metal out of the feature. This migration can damage an adjacent interconnect line, cause junction leakage, form unintended electrical connections, and disrupt electrical flow in the feature from which the metal migrates.
Accordingly, among the challenges facing integrated circuit device manufacturers is to minimize diffusion and electromigration of metal out of metal-filled interconnect features. This challenge becomes more acute as the devices further miniaturize, and as the features further miniaturize and densify.
Another challenge in the context of metal interconnect features is to protect them from corrosion. Certain interconnect metals, especially Cu, are more susceptible to corrosion.
Copper is a fairly reactive metal which readily oxidizes under ambient conditions. This reactivity can undermine adhesion to dielectrics and thin films, resulting in voids and delamination. Another challenge is therefore to combat oxidation and enhance adhesion between the cap and the Cu, and between structure layers.
To address these challenges the industry has employed a variety of diffusion barrier films as a cap over Cu and other metal interconnect features. Refractory metals and their alloys have been deposited in thin films by physical vapor deposition (PVD). SiN and SiC have been deposited for this purpose by chemical vapor deposition (CVD). A limitation of SiN and SiC is that they have a relatively high dielectric constant (k value), which tends to increase capacitance of the interconnect. An increase in capacitance can increase power dissipation due to resistance/capacitance coupling (RC delay), thereby limiting the performance.
In general, barrier or capping layer formation by blanket vapor deposition is expensive and time-consuming, as it involves multiple processing steps. The deposited films need to be patterned and etched, followed by resist removal. Some degree of misalignment is expected with lithographic patterning.
Electroless Co and Ni have been discussed as a protective layer over electrical interconnect lines in, for example, U.S. patent publication No. 2003/0207560.
Chemical mechanical polishing (CMP) is performed on a substrate prior to capping and following via formation to, for example, remove unwanted Cu overburden deposited during damascene processing and thereby planarize the surface. This CMP can cause traces of copper to be embedded or smeared onto the dielectric material. These traces of copper, if not removed, can contaminate the dielectric. The traces of Cu can have a detrimental effect on the selectivity of a Co-capping process by causing deposition of electroless Co on the dielectric between the Cu traces, which can result in junction leakage. An etchant is therefore employed in a pretreatment composition to either remove these traces of copper, undercut the dielectric on which they reside, or both.
According to conventional wet processing, sequences separate cleaning solutions are employed for cleaning of dielectric, and for cleaning of the metal. Dielectric cleaner lightly etches the dielectric surface in order to undercut metal traces embedded onto the dielectric during CMP. Metal cleaner removes surface oxides on Cu and any remaining traces of Cu embedded in the dielectric that were not removed during the dielectric cleaning step. A cleaner may be necessary to remove residues from Cu inhibitors such as benzotriazole (BTA) compounds used during CMP processing so that such residues do not interfere with effectiveness of activation, uniformity of activation and initiation, smoothness of cap deposition, adhesion of capping deposit, and thermal stability of the cap.